Freescale Semiconductor /MKV11Z7 /SIM /CLKDIV1

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLKDIV1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (000)OUTDIV5 0 (0)OUTDIV5EN 0 (000)OUTDIV4 0 (0000)OUTDIV1

OUTDIV5EN=0, OUTDIV4=000, OUTDIV5=000, OUTDIV1=0000

Description

System Clock Divider Register 1

Fields

OUTDIV5

Clock 5 Output Divider Value

0 (000): Divide-by-1

1 (001): Divide-by-2

2 (010): Divide-by-3

3 (011): Divide-by-4

4 (100): Divide-by-5

5 (101): Divide-by-6

6 (110): Divide-by-7

7 (111): Divide-by-8

OUTDIV5EN

OUTDIV5 Divider Control

0 (0): OUTDIV5 disabled

1 (1): OUTDIV5 enabled

OUTDIV4

Clock 4 Output Divider Value

0 (000): Divide-by-1.

1 (001): Divide-by-2.

2 (010): Divide-by-3.

3 (011): Divide-by-4.

4 (100): Divide-by-5.

5 (101): Divide-by-6.

6 (110): Divide-by-7.

7 (111): Divide-by-8.

OUTDIV1

Clock 1 Output Divider Value

0 (0000): Divide-by-1.

1 (0001): Divide-by-2.

2 (0010): Divide-by-3.

3 (0011): Divide-by-4.

4 (0100): Divide-by-5.

5 (0101): Divide-by-6.

6 (0110): Divide-by-7.

7 (0111): Divide-by-8.

8 (1000): Divide-by-9.

9 (1001): Divide-by-10.

10 (1010): Divide-by-11.

11 (1011): Divide-by-12.

12 (1100): Divide-by-13.

13 (1101): Divide-by-14.

14 (1110): Divide-by-15.

15 (1111): Divide-by-16.

Links

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